This invention relates to the testing of fully populated circuit boards while connected in an operating (live) system and, in particular, to apparatus and methods for testing these circuit boards so as to reduce the down time of the system.
The circuit boards to be tested in accordance with the invention are normally fully populated with circuit components (e.g., integrated circuits and the like) which were already tested for operability and functionality before being mounted on the circuit boards. Although the individual components mounted on a circuit board of interest were previously tested and found to be fully operational, it is possible that, in the course of mounting the components on a board, certain components and/or interconnections may become, or be rendered, defective (e.g., they may be shorted or opened). It is also possible that, as a function of time and under temperature or other operative stresses, certain components and/or connections may become defective and/or non-functional. This is problematic in applications where a very high degree of reliability is desired and/or necessary. Therefore, in many electrical systems, where a high degree of reliable operation is essential, it is necessary to continuously test the circuit boards to ensure their operability. This is also the case where the system includes a spare (duplicate or redundant) board for each circuit board. That is, the circuit boards and their duplicate circuit boards are required to be constantly tested for operability.
A problem in testing circuit boards while they are connected in an operating system (live or on-line) is that the operation of the system has to be interrupted. This is highly undesirable. Accordingly, it is an object of this invention to reduce the down time of the system when the circuit boards are being tested.